Integrated circuits, also referred to as “chips”, must have a multi-layer interconnection structure, including a plurality of interwoven conductive lines to electrically connect elements in the semiconductor layers. Different techniques are used to build this structure, depending on whether the chip is aluminum-based or copper-based. A problem that is encountered in building an aluminum interconnection structure is varying dielectric thickness. For a copper interconnection structure, however, a problem of varying copper thickness can be encountered.
Copper-based chips are produced, in part, using a damascene or dual-damascene process. In this process, the underlying dielectric material layer is patterned with open trenches that are created in the desired locations of the prospective conductive lines. A thick coating of copper that significantly overfills the trenches is deposited on the dielectric material, and chemical-mechanical planarization or polishing (CMP) is used to remove the copper to the level of the top of the insulating layer.
With successive layers of insulator and copper, the multilayer (5-10 metal layers or more) interconnection structure is created. Unfortunately, it has not yet been possible to equalize the rate at which copper is removed during CMP with the rate at which the dielectric material is removed, with the copper generally being removed more rapidly than the dielectric. Consequently, an area with more embedded copper lines will generally be removed more quickly, potentially leading to an uneven surface and uneven copper line thickness. In turn, this could affect the integrated-circuit performance in an unpredictable manner, because the electrical characteristics of the copper lines are affected by their thicknesses. More specifically, the thickness affects conductivity, capacitance, inductance, signal attenuation, and timing for a signal traveling through the structure.
With respect to the CMP process, ideally all of the dielectric would be uniformly exposed at the same moment, and the process would be brought to a stop at that moment. Sometimes, however, the dielectric layer is exposed in one region, but not exposed in another. The CMP process must continue until the dielectric is exposed across all regions. This causes some copper to be recessed relative to the dielectric (“dishing”, or local “step height”), and removal of dielectric (“erosion”, or global “step height”).
For aluminum-based chips, aluminum structures are constructed first, and then covered with dielectric. Typically, however, before CMP the topography of the dielectric layer roughly follows the topography of the underlying aluminum structures. Although CMP is used to create a flat top surface, the post-CMP top surface of the dielectric will tend to be lower where the dielectric is covering a low density of aluminum structure, and higher where a high density of aluminum structure is covered. This variation is undesirable because the distance between layers becomes uneven and unpredictable, adding an element of uncertainty to the electromagnetic effects between layers. Also, such variation results in yield loss, because of the greater depth of focus uncertainty added into the fabrication process. Individual chips may be nonfunctional due to either an unwanted short or unwanted open circuit. Dummy or “fill” elements are typically added to a layout to reduce variation in the vertical position of the dielectric top surface. Unlike the situation with respect to a copper-based chip, however, metal structure thicknesses are not affected.
Frequently, non-functional metal elements (“fill”) are added to the layout by the designer, thereby increasing the uniformity of the density of the metal pattern. This, in turn, prevents unevenness that could be caused by the CMP process as explained above.
Typically, after a preliminary layout, including fill, is completed, an optical proximity correction (OPC) program is executed to determine a set of mask aperture shape adjustments designed to enhance the effect of the masking process in photolithography. Running the OPC program is time-consuming, with the amount of time consumed, as well as the quality of the OPC solution, generally related to the spatial complexity of the preliminary layout. It is problematic if the spatial complexity of fill complicates and compromises the quality of the OPC solution for a given wire. Additionally, fill elements on a first layer can affect electrical characteristics of conductive lines on a second, typically neighboring, layer.
Other manufacturing steps for IC interconnects, specifically, the etching process, are strongly affected by the pattern context of a given manufactured wire. Thus, the chips actually produced by etch processes are more likely to match the design characteristics assumed in the Electronic Design Automation (EDA) tools, if the fill postulated by the EDA tools and used in the analyses performed by these tools is changed in a manner designed to minimize the effect on electrical characteristics.